Senior Heterogeneous Integration Engineer
Paradromics
2w ago
SeniorNeurology
Description
 <h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">About Paradromics</span></span></span></span></span></span></h2><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Brain-related illness is one of the last great frontiers in medicine, not because the brain is unknowable, but because it has been inaccessible. Paradromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution: the individual neuron. AI algorithms then decode this massive amount of brain-data, enabling the seamless translation of thought into treatments.</span></span></span></span></span></span></p><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Our first clinical application, the Connexus® BCI, will help people who are unable to speak, due to ALS, spinal cord injuries and stroke, to communicate independently through digital devices. However, the capabilities of our BCI platform go far beyond our first application. With the brain in direct communication with digital devices, we can leverage technology to transform how we treat conditions ranging from sensory and motor deficits to untreatable mental illness.</span></span></span></span></span></span></p><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">The Role</span></span></span></span></span></span></h2><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">We are looking for an exceptional scientist/engineer to bridge the gap between silicon microfabrication and complex, real-world systems. While many can build a MEMS device in a vacuum, we need someone who understands the physics of integrating those devices into heterogeneous material stacks without compromising performance.</span></span></span></span></span></span></p><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">You will span the disciplines of materials physics, thermomechanical simulation, and micro-assembly and testing to solve complex challenges in wafer-level and die-level bonding. You will be the primary technical owner of the interface between our core semiconductor devices and the macro-packaging world.</span></span></span></span></span></span></p><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">Responsibilities</span></span></span></span></span></span></h2><ul><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Lead the development of novel bonding processes (wafer-to-wafer, die-to-wafer) involving dissimilar materials.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Optimize protocols for various bonding processes including wafer bonding, diffusion bonding, laser bonding, and more, focusing on interface mechanics, intermetallic formation, and stress management.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Use FEA tools (COMSOL, ANSYS) to model thermal dissipation and perform thermomechanical analysis in multi-material stacks.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Oversee or execute cleanroom processes (lithography, deposition, etching) required to prepare surfaces for high-fidelity integration.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Utilize SEM, TEM, CSAM, and mechanical pull-testing to validate bond quality and reliability under thermal cycling.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Translate complex material requirements into specs for foundry partners or equipment vendors.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Collaborate with Electrical Engineering and Electrode Manufacturing teams to support infrastructure and integration needs.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Optimize development processes and translate them into manufacturing protocols.</span></span></span></span></span></span></li></ul><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">Required Qualifications</span></span></span></span></span></span></h2><ul><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Ph.D. or M.S. in Materials Science, Applied Physics, Mechanical Engineering, or Electrical Engineering.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">5+ years of hands-on experience in heterogeneous integration or advanced packaging.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Deep expertise in the physics and chemistry of adhesion and bonding with proven experience in at least two of the following: wafer bonding (fusion, anodic, eutectic), TLP (Transient Liquid Phase) bonding, or laser-assisted bonding.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">A portfolio of work demonstrating the integration of silicon devices with non-silicon materials (e.g., ceramics, glass, metals, polymers, or III-V semiconductors).</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Proficiency in finite element analysis for thermal and structural mechanics.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Hands-on cleanroom experiences, specifically regarding surface activation and planarization (CMP) for bonding.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Hands-on experiences and knowledge with mechanical and electrical testing instruments, and building customized test setups.</span></span></span></span></span></span></li></ul><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">Preferred Qualifications</span></span></span></span></span></span></h2><ul><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Familiarity with the requirements and testing of hermetic packaging for MEMS</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Familiarity with methods and instruments for package and interface integrity characterization.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Familiarity with polymer-to-inorganic material adhesion and testing.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Experience designing micro-heaters or managing high-heat-flux devices.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Background in academic labs known for microsystems (e.g., Stanford SNF/SNSF, MIT MTL, Michigan LNF).</span></span></span></span></span></span></li></ul><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">Why This Team?</span></span></span></span></span></span></h2><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Most MEMS roles stop at the dicing saw. This role begins where the fab ends. You will be solving the "packaging gap"—the critical bottleneck in modern hardware physics. If you enjoy the challenge of making materials stick together that usually refuse to, this is your home.</span></span></span></span></span></span></p><h2 style="line-height:1.38;margin-top:24px;margin-bottom:5px;"><span style="font-size:17pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:700;"><span style="font-style:normal;"><span style="text-decoration:none;">Location</span></span></span></span></span></span></h2><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Austin, TX (On-site)</span></span></span></span></span></span></p><hr><p style="line-height:1.38;margin-top:16px;margin-bottom:16px;"><span style="font-size:11pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Paradromics is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, or national origin.</span></span></span></span></span></span></p><br> 
Paradromics
BIOTECHNOLOGY
Brain Computer Interfaces
LocationTX - Austin
Open Jobs13
Neurology
View Company ProfilePipeline
Connexus Brain-Computer InterfaceN/A