Description

About ParadromicsBrain-related illness is one of the last great frontiers in medicine, not because the brain is unknowable, but because it has been inaccessible. Paradromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution: the individual neuron. AI algorithms then decode this massive amount of brain-data, enabling the seamless translation of thought into treatments. Our first clinical application, the Connexus® BCI, will help people who are unable to speak, due to ALS, spinal cord injuries and stroke, to communicate independently through digital devices. However, the capabilities of our BCI platform go far beyond our first application. With the brain in direct communication with digital devices, we can leverage technology to transform how we treat conditions ranging from sensory and motor deficits to untreatable mental illness. The RoleAs a Senior Digital Design Engineer, you will translate algorithms and system requirements into clear digital microarchitectures and high-quality, synthesizable RTL that forms the foundation of our silicon. You will own digital blocks from microarchitecture through RTL implementation and work closely with physical design across the RTL-to-GDS flow to deliver robust, production-quality designs, using implementation feedback to drive architecture and algorithm tradeoffs for best PPA.Rapid FPGA prototyping is a core part of this role: you will bring designs up early on FPGA to de-risk architectures, validate interfaces, and enable system-level integration and lab testing. You will own FPGA implementation end-to-end (synthesis, constraints, implementation, and timing closure), iterating quickly while keeping a clear eye on how designs will translate cleanly from FPGA to ASIC.<h2 style="line-height:1.38;margin-top:24px;margin-bottom:13px;">Responsibilities</h2><ul><li style="list-style-type:disc;">Define digital microarchitecture for datapaths, control, buffering, and interfaces.</li><li style="list-style-type:disc;">Write high-quality, synthesizable RTL for FPGAs and ASICs.</li><li style="list-style-type:disc;">Own FPGA implementation end-to-end: synthesis, timing/physical constraints, implementation, timing closure, and board-level debug.</li><li style="list-style-type:disc;">Translate DSP algorithms into efficient, real-time hardware pipelines.</li><li style="list-style-type:disc;">Produce clear interface specs, block diagrams, and timing documentation.</li><li style="list-style-type:disc;">Partner with physical design to refine RTL and microarchitecture based on synthesis and timing feedback.</li><li style="list-style-type:disc;">Contribute to verification planning and debug using waveforms, logs, and assertions.</li><li style="list-style-type:disc;">Support front-end checks (lint, CDC/RDC, constraint reviews).</li></ul><h2 style="line-height:1.38;margin-top:24px;margin-bottom:13px;">Required Education</h2>Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or equivalent experience.<h2 style="line-height:1.38;margin-top:24px;margin-bottom:13px;">Required Qualifications</h2><ul><li style="list-style-type:disc;">5+ years designing RTL for FPGAs and/or ASICs, including microarchitecture and ownership of a major block from spec to signoff.</li><li style="list-style-type:disc;">Deep proficiency in SystemVerilog/Verilog (or VHDL) for synthesizable RTL.</li><li style="list-style-type:disc;">Strong theoretical foundation in digital signal processing (i.e. filters, transforms, and sampling). </li><li style="list-style-type:disc;">Strong hands-on FPGA prototyping and bring-up experience (constraints, implementation, timing analysis, board debug).</li><li style="list-style-type:disc;">Experience translating DSP algorithms into efficient, real-time hardware pipelines.</li><li style="list-style-type:disc;">Experience with digital control of analog/mixed-signal IP, including ADC/DAC control, SPI/I²C, high-speed SERDES, and clocking/reset logic.</li><li style="list-style-type:disc;">Proven ability to develop microarchitecture from system requirements.</li><li style="list-style-type:disc;">Understanding of process-node tradeoffs and their impact on RTL and microarchitecture.</li><li style="list-style-type:disc;">Familiarity with front-end flows (synthesis, STA, lint, CDC/RDC).</li><li style="list-style-type:disc;">Strong debug skills using waveforms, logs, and implementation reports.</li><li style="list-style-type:disc;">Scripting in Python/Tcl/Perl for automation and analysis.</li></ul><h2 style="line-height:1.38;margin-top:24px;margin-bottom:13px;">Preferred Qualifications</h2><ul><li style="list-style-type:disc;">Experience proactively tuning RTL and microarchitecture to deliver ASIC-ready RTL that meets PPA targets in collaboration with physical design.</li><li style="list-style-type:disc;">Familiarity with SystemC or high-level behavioral modeling.</li><li style="list-style-type:disc;">Exposure to UVM/formal and SystemVerilog Assertions (SVA).</li><li style="list-style-type:disc;">Working knowledge of DFT (scan, MBIST/LBIST).</li><li style="list-style-type:disc;">Experience with common interfaces (AXI/APB, SPI, I²C, UART).</li><li style="list-style-type:disc;">Experience with silicon debug.</li><li style="list-style-type:disc;">Familiarity with neural signal processing or real-time data systems.</li></ul>Paradromics is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, or national origin.

Senior Digital Design Engineer (FPGA/ASIC)

Description

Paradromics

Pipeline