Electrical Engineer (Systems Generalist)

Neurology

Description

<p style="line-height:1.3800000000000001;text-align:center;"><span style="font-size:16pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Electrical Engineer (Systems Generalist)</span></span></span></span></span></span></p>&#160;<p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">About Paradromics</span></span></span></span></span></span></p><p style="line-height:1.3800000000000001;text-align:justify;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Brain-related illness is one of the last great frontiers in medicine, not because the brain is unknowable, but because it has been inaccessible. Paradromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution: the individual neuron. AI algorithms then decode this massive amount of brain-data, enabling the seamless translation of thought into treatments.&#160;</span></span></span></span></span></span></p>&#160;<p style="line-height:1.3800000000000001;text-align:justify;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Our first clinical application, the Connexus&#174; BCI, will help people who are unable to speak, due to ALS, spinal cord injuries and stroke, to communicate independently through digital devices. However, the capabilities of our BCI platform go far beyond our first application. With the brain in direct communication with digital devices, we can leverage technology to transform how we treat conditions ranging from sensory and motor deficits to untreatable mental illness.</span></span></span></span></span></span></p>&#160;<p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">The Role</span></span></span></span></span></span></p><p style="line-height:1.3800000000000001;margin-top:16px;margin-bottom:16px;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">The Electrical Engineer (Generalist) will own and support system-level electrical development across hardware, programmable logic, and mixed-signal domains. This role focuses on system integration, bring-up, debugging, and stabilization rather than solely PCB layout.</span></span></span></span></span></span></p><p style="line-height:1.3800000000000001;margin-top:16px;margin-bottom:16px;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Working closely with cross-functional teams&#8212;including FPGA, firmware, mechanical, and test engineers&#8212;this person will drive hardware systems from prototype through validation and early production. The ideal candidate is comfortable operating across digital, analog, power, and signal integrity domains and thrives in fast-paced, multidisciplinary environments.</span></span></span></span></span></span></p><br><p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Responsibilities</span></span></span></span></span></span></p><ul><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Lead system bring-up and stabilization across hardware and programmable logic platforms.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Debug FPGA-based systems at both the board and system level, collaborating with digital design teams.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Develop structured debug plans and execute root cause analysis across electrical, firmware, and system domains.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Analyze and optimize digital system architecture including clocking schemes, reset strategies, high-speed data paths, and timing considerations.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Evaluate and troubleshoot analog and mixed-signal subsystems including power regulation, grounding, EMI mitigation, and signal integrity.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Support integration of subsystems involving wireless power transfer, RF signaling, or optical communication links.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Develop Python-based tools for lab automation, instrument control, data capture, and validation workflows.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Support system-level validation, characterization, and field testing activities.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Contribute to technical trade studies and clearly communicate design trade-offs across teams.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Maintain organized documentation, debug records, and validation reports throughout development.</span></span></span></span></span></span></li></ul>&#160;<p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Required Education</span></span></span></span></span></span></p><ul><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Bachelor&#8217;s or Master&#8217;s degree in Electrical Engineering or related field, or equivalent practical experience.</span></span></span></span></span></span></li></ul>&#160;<p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Required Qualifications</span></span></span></span></span></span></p><ul><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Demonstrated ownership of system bring-up and stabilization across hardware and programmable logic platforms.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Strong experience debugging FPGA-based systems at the board and system level.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Solid understanding of digital system architecture including clocking, resets, high-speed data paths, and timing constraints.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Working knowledge of analog and mixed-signal fundamentals including power regulation, signal integrity, grounding, and EMI principles.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Experience supporting or integrating systems involving wireless power transfer, RF signaling, or optical communication links.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Proficiency in Python for test automation, lab control, data analysis, or validation infrastructure.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Ability to develop structured debug plans and drive root cause analysis across multiple technical domains.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Experience supporting system-level validation, field testing, or early production hardware.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Strong ability to synthesize cross-domain findings and communicate technical trade-offs clearly.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Comfort working in fast-paced hardware development environments with evolving requirements.</span></span></span></span></span></span></li></ul><br><p style="line-height:1.3800000000000001;"><span style="font-size:13.999999999999998pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Preferred Qualifications</span></span></span></span></span></span></p><ul><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Experience collaborating closely with FPGA/RTL design teams.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Exposure to regulated hardware environments (medical, aerospace, industrial, etc.).</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Familiarity with high-speed interfaces (e.g., SERDES-based links, DDR memory systems).</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Experience designing or supporting hardware test infrastructure.</span></span></span></span></span></span></li><li style="list-style-type:disc;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#000000;"><span style="font-weight:400;"><span style="font-style:normal;"><span style="text-decoration:none;">Background in multidisciplinary system integration efforts.</span></span></span></span></span></span></li></ul><br><p style="line-height:1.3800000000000001;"><span style="font-size:12pt;font-variant:normal;white-space:pre-wrap;"><span style="font-family:Arial, sans-serif;"><span style="color:#003bae;"><span style="font-weight:400;"><span style="font-style:italic;"><span style="text-decoration:none;">Paradromics is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, or national origin.</span></span></span></span></span></span></p><br>&#160;
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